1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device having a shallow, heavily doped source/drain layer, which is formed by applying selective deposition of a silicon layer, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, a large-scaled integrated circuit (LSI) in which a large number of transistors and resistors are coupled to constitute an electric circuit and integrated on one chip is often used in the important portion of a computer or communication equipment.
Selective chemical vapor deposition (selective CVD) has been recently examined as an LSI technology. Selective CVD is applied to, e.g., an elevated source/drain or self-aligned contact technique. With this technique, a silicon layer serving as a source/drain impurity diffused layer or a direct contact layer having excellent characteristics can be formed in one selective growth.
Typical selective CVD for a silicon layer as shown in FIGS. 1A and 1B is conventionally known, in which CVD using an Si/Cl/H.sub.2 reduction reactive gas, particularly, dichlorosilane (SiH.sub.2 Cl.sub.2) source gas added with hydrochloric acid (HCl) gas and H.sub.2 gas is used, and an insulating film 2 such as a silicon oxide film (SiO.sub.2) and a silicon nitride film (Si.sub.3 N.sub.4) is used as a mask to selectively grow a silicon layer 3 on the exposed surface of a silicon substrate 1 in the opening portion of the insulating film. Impurity doping into the selectively grown silicon layer 3 is performed by mixing a gasified compound containing impurity atoms with a reactive gas.
In the selective CVD method of this type, however, gas species capable of obtaining a satisfactory selectivity are limited, and the silicon layer 3 is normally epitaxially grown. Therefore, as shown in FIG. 1B, a facet 4 having a (111) plane is normally formed in the silicon layer 3.
In addition, when a shallow impurity diffused layer is to be formed, a silicide film is normally formed to decrease the resistance of the impurity diffused layer. More specifically, a titanium film is formed on the impurity diffused layer by sputtering, and annealing is performed by RTA (Rapid Thermal Annealing) at 700.degree. C. for 30 seconds, thereby forming a titanium silicide film.
Since the silicide film is formed upon reaction between a refractory metal film as a silicide film and silicon in the impurity diffused layer, the silicon in the impurity diffused layer is consumed. For this reason, if the depth of the impurity diffused layer is small, the effective thickness of the impurity diffused layer must be increased by selectively growing a silicon layer on the impurity diffused layer.
However, if the silicon layer is obtained as an epitaxially grown film, the facet 4 is formed as in the silicon layer 3 in FIG. 1B. Therefore, the end portion of the silicon layer becomes thinner to degrade the effect of deposition of the silicon layer.
To avoid this problem, an amorphous silicon layer may be selectively deposited. In this case, however, the deposition temperature or the substrate temperature must be decreased, so a satisfactory deposition rate cannot be ensured.
The conventional direct contact technique has another problem caused by facet formation. This will be described below with reference to the manufacturing steps shown in FIGS. 2A to 2C.
As shown in FIG. 2A, BF.sub.2.sup.+ is ion-implanted in the surface of a p-type silicon substrate 11, thereby selectively forming an n-type impurity diffused region 13. After an insulating film 12 is deposited on the p-type silicon substrate 11, an opening portion (contact hole) is formed in this insulating film 12.
As shown in FIG. 2B, a single-crystal silicon layer 14 serving as an electrode containing an impurity is buried in the opening portion by selective epitaxy.
As shown in FIG. 2C, a polysilicon layer is deposited on the entire surface and patterned to form a wiring layer 15.
When this method is used, it becomes difficult to smoothly bury the opening portion because a facet 16 having a (111) plane is formed in the single-crystal silicon layer 14 as an epitaxially grown layer.
In addition, to deposit the polysilicon layer serving as the wiring layer 15, the resultant structure is conveyed from the selective deposition apparatus to the polysilicon layer deposition apparatus while being exposed to air. For this reason, a native oxide film is formed on the upper portion of the single-crystal silicon layer 14, resulting in an increase in contact resistance with respect to the wiring layer 15. When the resultant structure is exposed to air, no satisfactory selectivity can be obtained because of a contaminant such as dust, and a short circuit may occur in wiring layer because silicon is deposited on the insulating film 12 in some cases.
Elements become finer as the degree of integration of a semiconductor device is increased. Therefore, when the gate length of a MOS transistor is decreased, the so-called short channel effect such as a decrease in threshold voltage poses a serious problem. To prevent this short channel effect in the MOS transistor, it is conventionally required to decrease the diffusion depth of a source/drain diffused layer. In addition, to maintain a low resistance, it is required to increase the concentration of the source/drain layer.
These requirements are particularly needed at the end portion of a source/drain diffused layer. More specifically, as the elements become finer, it becomes more preferable that the end portion of the source/drain layer have a high concentration and a small diffusion depth. To cope with these requirements, an LDD (Lightly Doped Drain) structure is conventionally adopted as a source/drain diffusion layer structure.
The LDD structure is obtained by the following method. After a gate electrode is formed, ion implantation is performed at a low acceleration voltage and a low dose to form a shallow, lightly doped source/drain layer. Subsequently, a side-wall gate oxide film is formed. Thereafter, ion implantation is performed at a high acceleration voltage and a high dose to form a deep, heavily doped source/drain diffused layer. To further decrease the resistance, a silicide film is normally formed on the source/drain diffused layer.
To make the elements finer by using the LDD structure, the acceleration voltage of ion implantation of the impurity into the gate electrode end portion must be decreased, or the dose amount must be decreased.
However, when the acceleration voltage of ion implantation is decreased to form a shallow, lightly doped source/drain layer, the beam current in ion implantation decreases, resulting in a degradation in throughput.
When the acceleration voltage is low, the influence of channeling in the profile of ion implantation becomes conspicuous, so no shallow diffused layer can be formed even by decreasing the acceleration voltage. When the acceleration voltage is lower, the surface of the substrate is undesirably sputtered.
As described above, ion implantation has a limit in formation of shallow junction in principle. More specifically, the distribution of the implanted impurity largely depends on the acceleration energy in ion implantation. To obtain a shallow junction, a shallow ion implantation distribution must be obtained.
The implantation depth is almost inversely proportional to the mass of ions. For this reason, in formation of a p.sup.+ -layer, for which no appropriate impurity is present except for boron, it becomes more difficult to obtain a shallow ion implantation distribution. Conventionally, to effectively decrease the acceleration energy, BF.sub.2.sup.+ ions are used.
In this method, a source/drain layer is formed by known ion implantation. More specifically, a silicon oxide film and a polysilicon film are sequentially formed on an element region isolated by an element isolation insulating film formed on a silicon substrate. A resist pattern is used as a mask to perform patterning, thereby forming a gate oxide film and a gate electrode.
The gate electrode is used as a mask to implant BF.sub.2.sup.+ ions. The implanted BF.sub.2.sup.+ ions repeat collision in the silicon substrate and are distributed around the peak depth depending on the acceleration energy. Thereafter, annealing is performed in a nitrogen atmosphere at 850.degree. C. for 30 minutes to diffuse boron in the silicon substrate and activated, thereby forming a diffused layer serving as a source/drain region.
Even with this method, however, it is difficult to form a diffused layer having a depth of 0.1 .mu.m or less. For example, when BF.sub.2.sup.+ ions are implanted at an acceleration voltage of 20 keV and a dose of 5.times.10.sup.15 cm.sup.-2, a diffusion layer depth x (width of a region having a boron concentration of 1.times.10.sup.17 cm.sup.-3 or more) is 0.125 .mu.m immediately after ion implantation, or 0.175 .mu.m after annealing in the nitrogen atmosphere at 850.degree. C. for 30 minutes.
To form a fine element of 1 G-bit DRAM, which has a channel length of about 0.1 .mu.m, a shallow diffused layer having a depth of 0.1 .mu.m or less is required. However, such a diffused layer can be hardly realized by the conventional method. Additionally, when the dose for ion implantation is decreased, the parasitic resistance of the MOS transistor undesirably increases.
To form a shallow end portion of the source/drain diffused layer having a high concentration, another method is used in which, after a side-wall gate oxide film is formed, a thin film containing an impurity is deposited, and this thin film is used as a diffusion source to perform solid phase diffusion, thereby forming a source/drain diffused layer.
More specifically, a method is proposed in which, from a gas containing an impurity, the impurity is absorbed or diffused in the surface of a silicon substrate, or an impurity-doped silicon film containing an impurity is deposited, and the impurity is diffused into the silicon substrate by a heat energy or the like. For example, diborane (B.sub.2 H.sub.6) is thermally decomposed and absorbed by the silicon surface, and diffused into the silicon substrate.
With this method, the boron concentration in the diffused layer can be increased by performing annealing at a higher temperature. The depth of the diffused layer is determined by two factors, i.e., the annealing temperature and time after adsorption. More specifically, an increase in depth of the diffused layer, which is caused by an increase in annealing temperature, can be prevented by shortening the annealing time. Therefore, this method can be effectively used to form a shallow diffused layer having a high concentration.
With the method using thermal decomposition of an impurity, however, the impurity is also adsorbed by regions other than the silicon surface. This impurity layer adsorbed by the regions other than the silicon surface must be removed in post-processing.
In thermal decomposition of diborane or a method of diffusing an impurity from a material as a diffusion source using a B-doped silicon film using diborane and silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6), a native oxide film is formed when the silicon surface on which the diffused layer is to be formed is exposed to air, which impedes diffusion of the impurity. For this reason, the surface of the silicon substrate must be cleaned before the material serving as a diffusion source is formed.
Since the distribution of boron after annealing is determined in accordance with the complementary error function, the boron concentration near the junction boundary becomes lower than the surface concentration, resulting in an increase in resistance of the diffused layer. For example, under conditions for realizing a diffusion layer depth of 0.075 .mu.m, the sheet resistance value becomes 450 .OMEGA./.quadrature..
In this method, the impurity concentration immediately below the side-wall gate oxide film particularly becomes low at the end portion of the gate electrode, and the region having the low impurity concentration serves as the series resistance for the transistor. For this reason, the parasitic resistance increases.
When a method of forming a silicide film on the source/drain diffused layer is used, a certain diffusion layer depth must be ensured before formation of the silicide film. The reason for this is as follows. Generally, to form a silicide film, a method is used in which a refractory metal film is formed on a silicon substrate by sputtering, and the refractory metal film is caused to react with silicon in the source/drain diffused layer. This is because the silicon in the source/drain diffused layer is consumed during formation of the silicide film to decrease the diffusion layer depth.
In addition, another reason can also be considered. That is, three-dimensional patterns are formed at the boundary between the metal layer and the source/drain diffused layer. Because of these three-dimensional patterns, point defects are diffused into the substrate beyond the source/drain diffused layer upon reaction during formation of the silicide film, resulting in a degradation in junction characteristics.
To solve these problems, a method called an elevated source/drain method is proposed. In this method, after a source/drain diffused layer is formed by ion implantation, a silicon layer is selectively grown to elevate the level of the source/drain diffused layer. According to this method, the silicide technique can be applied without increasing the diffusion layer depth. However, since silicon selective growth is additionally performed, the number of manufacturing steps is undesirably increased.
If the selectively grown silicon film is an epitaxially grown film, a facet different from that of the central portion is formed at the end portion, as shown in FIG. 1B. In this case, the effective thickness at the end portion becomes smaller to cause a degradation in junction characteristics. If the silicon film to be elevated is undoped, an impurity of the same type as that for the diffused layer is ion-implanted to decrease the resistance of the silicon film. In this case, the amount of impurity implanted from the thin end portion increases to cause a degradation in reliability of the transistor.
To form a shallow diffused layer, a silicon film on an SOI substrate can be made thinner. In this case, the entire silicon film is converted into a depletion layer. Therefore, the short channel effect of a MOSFET can be prevented, and the current driving capability can be improved.
In the conventional method of forming a MOS transistor using an SOI substrate, an element isolation insulating film is formed on the SOI silicon film of the SOI substrate (an SOI silicon film is formed on a silicon support base interposing an SOI insulating film therebetween). A gate electrode consisting of an impurity-doped polysilicon film and a tungsten silicide film is formed, with a gate oxide film intervening therebetween, on an element formation region surrounded by the element isolation insulating film. The side wall and the upper surface of this gate electrode is covered with a silicon nitride film, thereby forming a gate portion.
After the gate portion is used as a mask to implant impurity ions, annealing is performed to activate the impurity ions, thereby forming a source/drain diffused layer.
However, this MOS transistor forming method has the following problems. In this forming method, ion implantation is performed to form the source/drain diffused layer. Therefore, a concentration profile representing that the impurity concentration gradually decreases in the lateral direction is formed in the source/drain diffused layer from the lower portion of the side-wall silicon nitride film to the gate edge.
For this reason, the resistance of the source/drain diffused layer increases as a whole, and the parasitic resistance between two source/drain diffused layers increases, resulting in a degradation in current driving capability. This problem becomes more serious as the thickness of the SOI silicon film becomes smaller.
In addition, assume that the semiconductor film of the SOI substrate is formed of silicon, as in the above MOS transistor. In this case, particularly, in an n-channel MOS transistor, when the drain voltage is increased in a state wherein the gate voltage is zero or the MOS transistor is kept off, a small leak current is generated to flow a subthreshold current.
As a result, impact ionization is caused by the subthreshold current to generate holes. The holes are accumulated below the channel to increase the potential. This causes a phenomenon for inducing electron injection from the source. Such a phenomenon causes a decrease in source/drain breakdown voltage when the transistor is in an OFF state. In addition, the subthreshold characteristics are also degraded.
As described above, in the conventional technique for selectively forming a silicon layer, a facet is formed to adversely affect post-processing.
In addition, in the conventional MOS transistor technology, when elements are made finer using the LDD structure, the resistance of the source/drain diffused layer increases to cause an increase in parasitic resistance.
Furthermore, when a source/drain diffused layer is formed by solid phase diffusion, the concentration in the source/drain diffused layer at the end portion of the gate electrode is decreased, resulting in an increase in parasitic resistance.